1. Field of the Invention
This invention relates generally to semiconductor manufacturing and, in particular, to preparing a cross section of a semiconductor chip for analysis.
2. Description of the Related Art
Failure analysis and sample preparation is an important tool in providing a detailed inspection of the physical characteristics of an integrated circuit (IC) fabricated on a semiconductor chip (IC chip). With the structure of integrated circuits decreasing in size and becoming more complex, electron microscopy has emerged as a critical tool for highly site-specific failure analysis. More particularly, an important issue is the analysis of via and contact failure between layers in an integrated circuit, which is one of the most common inspections in semiconductor manufacturing.
Physical characteristics of via and contact plugs provide critical factors in determining the overall performance of an IC chip. These physical characteristics are directly linked to the properties related to electrical conductivity of the via and contact plug. Some critical factors for via and contact properties include grain structure, barrier metal layer coverage and plug critical dimensions.
One important aspect of the failure analysis is to be able to gauge process integrity through images taken by a high resolution stereo scanning microscope. However, current techniques for preparing the sample tend to mask the textural properties, i.e., grain structure, of the feature by smearing the interconnect. Reactive Ion Etching (RIE) is one technique that may be used to prepare the sample. One shortcoming of RIE is that RIE requires hazardous chemicals as well as fume hoods. Of course, the chemicals must be disposed of once used. Thus, the current techniques for viewing the grain structure of an interconnect is expensive and hazardous.
As a result, there is a need to solve the problems of the prior art to safely and inexpensively evaluate the structural integrity of contacts of a semiconductor device.